The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device including a driver sequentially performing over-driving and normal driving operations.
In general, in a semiconductor memory device, when it is necessary to raise a predetermined node to a target level as quickly as possible, a method of over-driving the node higher than the target level in an initial operation is often used.
As an example, a sensing amplifier sensing a bit line pair amplifies the bit line pair with drive voltages respectively supplied from a pull-up drive node and a pull-down drive node. Conventionally, in order to rapidly sense and amplify a bit line pair, a voltage of a level higher than a core voltage VCORE, e.g., a power voltage VDD, is initially supplied to a pull-up drive node to be over-driven, and the core voltage VCORE is supplied to the pull-up drive node after the bit line pair are sufficiently sensed. That is, the pull-up drive node of the sensing amplifier is initially connected to a power voltage VDD terminal and then connected to a core voltage VCORE terminal after a predetermined time.
However, as a current that previously flowed at the power voltage VDD terminal flows into the core voltage VCORE terminal when the pull-up drive node is connected to the core voltage VCORE, the level of the core voltage VCORE may be raised.
The level rising of a core voltage VCORE due to such over-driving will be described with reference to FIG. 1. A sensing and amplifying operation of a bit line pair may be divided into an over-driving interval ‘A’ at which a power voltage VDD is supplied to a pull-up drive node and a normal driving interval ‘B’ at which a core voltage VCORE is supplied to the pull-up drive node.
At this time, due to the power voltage VDD applied to the pull-up drive node, the level of the core voltage VCORE may be raised higher by ΔV1 than a target value at the time when normal driving is started. In order to prevent leakage of a transistor or stabilize a level of the core voltage VCORE, the raised core voltage VCORE may be discharged through a transistor with a very small size. However, its discharge effect is extremely insignificant, and therefore, discharge is made by ΔV2 smaller than ΔV1. As a result, the level of the core voltage VCORE may be practically maintained as a level higher than the target value.
In order to solve such a problem, there has been suggested a structure in which a conventional discharge circuit forcibly dropping a core voltage VCORE to a target level after over-driving is connected to an output terminal of a core voltage driver.
That is, the conventional discharge circuit includes a pull-down transistor connected to the output terminal of the core voltage driver. When a core voltage VCORE is higher than a target voltage, comparing the core voltage with the target voltage during a predetermined time after over-driving, the core voltage VCORE is discharged using the pull-down transistor.
However, in the conventional discharge circuit having such a configuration, since the discharge amount of the core voltage VCORE is determined depending on the size of the pull-down transistor, it is difficult to uniformly maintain the core voltage VCORE as the target level.
That is, as shown in (a) of FIG. 2, when the size of the pull-down transistor is large, the core voltage is excessively discharged, and thus, the level of the core voltage VCORE may fall lower than a target core voltage Target VCORE. In this case, since the core voltage driver again raises the level of the core voltage VCORE in order to set the core voltage VCORE to a target level, a ringing phenomenon may occur, in which the level of the core voltage VCORE oscillates during a discharge interval ‘C’ at which the discharge circuit is operated after over-driving. Current consumption may also be increased.
On the other hand, when the size of the pull-down transistor is small as shown (b) of FIG. 2, the core voltage VCORE is not sufficiently discharged, and therefore, the level of the core voltage VCORE may be maintained higher than the target level.
These problems may be improved through size tuning of the pull-down transistor, discharge time tuning of the core voltage and response speed tuning of the discharge circuit in failure analysis, which may result in increased time and costs.
The aforementioned problems frequently occur because an amount of over-driving current is changed corresponding to the level fluctuation of a power voltage VDD.
That is, if the level of the power voltage VDD raises, the amount of over-driving current increases, and if the level of the power voltage VDD falls, the amount of over-driving current decreases. However, in the conventional discharge circuit, the discharge amount of the core voltage VCORE is fixed. For this reason, if the discharge amount is relatively small when the level of the power voltage VDD rises, the level of the core voltage VCORE may rise higher than the target level. If the discharge amount is relatively large when the level of the power voltage VDD falls, the level of the core voltage VCORE may fall lower than the target level.
As described above, when the level of a core voltage VCORE is changed corresponding to the level fluctuation of a power voltage VDD, reliability of a circuit using the core voltage VCORE may be lowered.